CHEN Jianju; PENG Shuping; DENG Shuling; ZHOU Wen; FAN Zhiqiang; ZHANG Xiaojiao

doi:10.7498/aps.74.20250849

Abstract

By using the first-principles method based on density functional theory and non-equilibrium Green’s function, the transport properties of 5-nm two-dimensional SiC field-effect transistors with asymmetric metal phase 1T-MoS₂ sources and Pd drain electrodes are investigated. The influence mechanism of increasing the electrode layers of 1T-MoS₂ and reducing the working electrical compression on the device performance is systematically analyzed. The Schottky barriers extracted from the zero bias and zero gate voltage transport spectra show that the valence band maximum of SiC in the channel regions of MFET, BFET and TFET are closer to the Fermi level after the source drain electrode has been balanced. Therefore, these three devices belong to P-type contact, and the height of the hole Schottky barrier increases with the increase of the number of 1T-MoS₂ layers in the source electrode, which are 0.6, 0.76, and 0.88 eV, respectively. In addition, the increase of 1T-MoS₂ layers will also lead to the increase of the density of states in the source electrode, thereby improving the transport coefficient at the band edge. The effects of the two on the transport capacity of the device are opposite, and there is a competitive relationship. The transfer characteristics of devices show that the wide band gap of SiC can significantly suppress the short channel effect, so that all devices can meet the requirements of Off-state. More importantly, the subthreshold swings of all devices at an operating voltage of 0.64 V are all close to the physical limit of 60 mV/dec. The ON-state currents of MFET, BFET and TFET can reach 1553, 1601 and 1702 μA/μm under the more stringent IRDS HP standard, and the three performance parameters, i.e. intrinsic gate capacitance, power-delay product and delay time, can greatly exceed the standards in the international road map of equipment and systems (IRDS) for high-performance devices. In addition, the working voltage of MFET can be reduced to 0.52 V, and the corresponding power-delay product and delay time are as low as 0.086 fJ/μm and 0.038 ps, which are only 14% and 4% of the IRDS standard. The asymmetric source drain electrode design strategy proposed in this work not only solves the problems about low On-state current and short channel effect restricting Off-state current of existing two-dimensional material field-effect transistors, but also provides an important solution for developing ultra-low power nano electronic devices in the post Moore era.

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Corresponding author: FAN Zhiqiang, zqfan@csust.edu.cn ; ZHANG Xiaojiao, xjzhang@hutb.edu.cn

Funds: Project supported by the National Natural Science Foundation of China (Grant No. 12074046).

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DownLoad: Full-Size Img PowerPoint

	C_g/ (fF·μm^–1)	PDP/ (fJ·μm^–1)	τ/ps
IRDS标准	0.39	0.49	0.96
MFET (V_DD = 0.64 V)	0.150	0.061	0.064
BFET (V_DD = 0.64 V)	0.155	0.063	0.064
TFET (V_DD = 0.64 V)	0.134	0.055	0.051
MFET (V_DD = 0.60 V)	0.146	0.071	0.056
MFET (V_DD = 0.56 V)	0.138	0.078	0.043
MFET (V_DD = 0.52 V)	0.142	0.086	0.038

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Vol. 74, Issue 19 - 2025-10-05

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